on the input is used
to improve circuit
stability. To prevent
damaging the Class
F operation, the λ/4
bias line is placed at
the outer side of the
network rather than
at the drain or gate
port of the transistor.
LOAD PULL/SOURCE PULL
The Class F PA design is biased with
a gate voltage of -2.8 V and a drain voltage of 28 V. The input power level is set
to 26 dBm. The load pull/source pull
simulation using Cree’s CGH40010
large signal transistor model is carried
out with Agilent’s Advanced Design
System (ADS) software. The objective is to maximize PAE with a high
output power. In this setup, the optimized source and load impedances at
the fundamental and second harmonics are determined. The simulation is
performed as follows:
1. Set the fundamental source impedance at a default value and
perform a fundamental load pull
simulation to determine the optimum fundamental load impedance
(ZL_fund). With a load impedance
of ZL_fund, perform a fundamental
source pull simulation to obtain
the optimum fundamental source
impedance (ZS_fund). After several
iterations, the optimum fundamental impedances are found to
be ZS_fund of ( 9.1-j1) Ω and ZL_fund
of ( 12. 5+j15.8) Ω.
2. Perform harmonic load pull simulations with ZS_fund and ZL_fund. In
this simulation, only the second
harmonic is considered and the
impedance value is restricted to
be purely reactive. The optimum
second harmonic load impedance
(ZL_2nd) is j120 Ω.
3. Perform harmonic source pull simulation. The optimum second harmonic source impedance (ZS_2nd)
is -j18.3 Ω.
Design of the input and output
matching network can be conducted
with the optimized impedance values.
The design approach has been report-
ed in many experimental works. 12, 13
Figure 2 shows the simulated drain
quent simplified vision10, 11 not only
significantly reduce the complexity
of the Volterra series model, but also
make the extraction of model param-
eters more flexible.
This article describes the design of
a Class F 2.12 GHz transmitter PA using Cree’s CGH40010 GaN HEMT.
The input and output matching networks are designed to optimally approximate the fundamental and second harmonic impedances obtained
in source and load pull simulations.
The simplified second-order dynamic
deviation reduction-based Volterra
series model10, 11 is used to improve
linearity. Both techniques optimize
the PA’s intrinsic efficiency-linearity
tradeoff. Experimental results with
a 20 MHz 4-carrier WCDMA signal
and a 20 MHz LTE signal reveal that
the digital predistorted Class F PA
achieves high efficiency and excellent
linearity at an average output power of
33. 3 dBm.
CLASS F POWER AMPLIFIER
With an infinite number of harmonic terminations, 100 percent
drain efficiency is theoretically achievable with square voltage and half-rec-tified sine current for Class F operation. However, it is not practical in a
realistic design to consider an infinite
number of harmonic terminations. In
this work, only the fundamental and
second harmonic impedances are considered. The topology of the circuit is
shown in Figure 1.
The output matching network
presents a short at the second harmonic and conjugately matches the
transistor’s fundamental output impedance to 50 Ω. The input matching
network provides the proper second
harmonic impedance at the transistor’s gate to improve efficiency and
provides an impedance match with
50 Ω at the fundamental. A resistor
s Fig. 1 Circuit topology of the Class F power amplifier.
RF IN RF OUT