Phase-Locked Loops Enable
Phase Alignment and Control
Ian Collins and Kazim Peker
Analog Devices Inc., Norwood, Mass.
Phase resynchronization and phase adjust features place phase-locked loop synthesizers into
known phase states. This enables many applications and greatly simplifies calibration.
As the name suggests, a phase- locked loop (PLL) uses a phase detector to compare a feedback signal with a reference signal,
locking the phases of both signals together. While this property has many applications, PLLs today are most commonly used
in frequency synthesis, generally as local
oscillators (LO) in frequency up- and downconverters or clocks for high speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC).
Until recently, little attention was paid to
the behavior of phase in these circuits, but
with a growing demand for efficiency, bandwidth and performance, RF engineers must
devise new techniques to improve spectral
and power efficiency. Repeatability, predictability and adjustability of the phase of a
signal all play an increasingly important role
in modern communication and instrumentation applications.
It is meaningless to refer to a phase measurement unless it is relative to another signal or to the original phase. For example, a
vector network analyzer (VNA) phase measurement of a two-port network, such as an
amplifier, relates the output phase to the
input phase (∠S21) or the phase of the reflected signal to the incident signal (∠S11).
For a PLL synthesizer, a phase measurement
relates to the input reference phase or compares the phase of one signal to another.
The “holy grail” or ideal state for any phase
measurement is to be at a precisely desired
value compared to the original phase. How-
ever, non-idealities such as nonlinearities,
temperature differences and manufacturing
variances mean that phase is among the
more variable of properties in signal genera-
tion. In this article, the term “in phase” refers
to signals that have precisely the same am-
plitude and timing properties, and “deter-
ministic phase” means that the phase offset
between them is known and predictable.
A high speed oscilloscope is a relatively
intuitive way to compare output phase to a
reference phase. To be visible, the input and
output phases generally must be integer
multiples of each other, a relatively common
case in many clocking circuits. For integer-N PLLs, the relationship between the input
frequency REFIN and the output frequency
RFOUT is generally deterministic and repeatable. Scope probes are placed on both the
REFIN and RFOUT ports, taking care to only
capture the signal when the phase has settled. A sophisticated oscilloscope, such as
the Rohde & Schwarz RTO1044, allows the
event trigger to activate only when a specific
digital pattern has been written to the PLL
device and a rising edge from the known
signal is present. Since there may be a delay
between writing the digital pattern and when
the final signal settles, some delay must be
inserted between the two events, which is a
capability provided in the RTO1044.