in the expected total noise contribution from the ADC for speci;c
frequency offsets from the input
signal (see Figure 6).
This analysis matches typical observations. For example, as the signal
input frequency increases, the clock
noise increases by 20log(FIN/FS).
Depending on the actual setup, the
far-end noise ;oor increases above
the ADC thermal noise, and a broad
noise ;oor increase is observable (see
Figure 4). Similarly, the clock noise
contribution reduces as the input signal amplitude is decreased.
Using the aperture jitter pro;le
information of the TI ADC32RF45,
along with the phase noise information of both the clock and input
signal generators, the total noise is
calculated for a clock frequency of
3 GSPS with an input signal of 1.8
GHz at -1 dBFS amplitude. The result in Figure 7 shows a very close
match, considering that other contributors such as power supply noise
and temperature are not included.
1. T. Neu, “Clock Jitter Analyzed in the Time
Domain, Part 2,” Texas Instruments Analog
Applications Journal (SLYT389), 4Q 2010.
2. T. Neu, “How Unmatched Impedance at
the Clock Input of an RF ADC Affects SNR
and Jitter,” Texas Instruments Analog Applications Journal (SLYT679), 3Q 2016.
3. T. Neu, “Impact of Sampling Clock Spurs
on ADC Performance,” Texas Instruments
Analog Applications Journal (SLYT338), 3Q
4. R. Keller, “Signal Chain Basics #45: Is High-Speed ADC Clock Jitter Being Over-Spec-i;ed for Communication Systems?” Planet
Analog, September 2010.
5. T. Neu, “Clocking the RF ADC: Should You
Worry About Jitter or Phase Noise?” Texas
Instruments Analog Applications Journal
(SLYT705), 1Q 2017.
4.Account for the amplitude of
the input signal. The clock noise
contribution is reduced when the
signal amplitude is less than the
ADC full scale. For example, a
3 dB back-off (Ain = - 3 dBFS) reduces the noise power in each
frequency bin by 3 dB.
5. Calculate the total ADC noise
contribution by adding the ADC
thermal noise. The last step is
to combine the ;nal clock noise
with the inherent thermal noise
of the data converter. This results
Fig. 7 Comparison of calculated data converter noise and
FFT measurement (262, 144 points, 100x averaging, FIN = 1 GHz
and FS = 3 GSPS).
1000 100 10 1 0.1 0.01
Frequency Offset (MHz)
Fig. 6 Total ADC noise after adding data converter thermal
Shifted, Combined Clock Noise
3. Adjust the clock noise by accounting for the signal input frequency.
The noise in each frequency bin is
shifted by Equation 2
PNFIN= PNC+ 20log FIN FS ⎛⎝⎜ ⎞⎠⎟ (2 )
where FIN is the signal input frequency and FS is the ADC sampling rate. As the signal input frequency increases, SNR degradation due to clock noise increases